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Ryzen 9000/7000 Memory/Infinity Fabric general information
🕑 Added 2024-11-02 03:39:45 +0000 UTCInfinity Fabric (FCLK)
clocks: 2000-2200 MHz
tends to scale negative with VSOC past a certain point
max clocks usually at 1.0-1.2V
has error correction. If slightly unstable will cause stuttering, hitching and audio cuts
lazy way for "stability":
just set FCLK 66MHz bellow max "functional"
for example: if 2233MHz boots and kinda runs then 2166MHz at same voltages should be 100% stable.
UCLK = MCLK / "1:1 mode" refers to memory controller and PHY/DRAM config. It DOES NOT SYNCHRONIZE THE INFINITY FABRIC.
in 1:1 mode optimal FLCK is either FCLK = 2/3 UCLK or FCLK at least 66MHz higher than 2/3 UCLK.
examples:
DDR5-6000 1:1 mode + 2000MHz FCLK = GOOD
DDR5-6000 1:1 mode + 2066MHz FCLK = BAD
DDR5-6000 1:1 mode + 2100MHz FCLK = GOOD
DDR5-6200 1:1 mode + 2066MHz FCLK = GOOD
DDR5-6200 1:1 mode + 2100MHz FCLK = BAD
DDR5-6200 1:1 mode + 2166MHz FCLK = GOOD
FCLK is less important than UCLK
example:
DDR5-6000 1:1 mode + 2200FLCK is slower than DDR5-6200 1:1 mode + 2066 FCLK
in 2:1 mode FCLK can sync to UCLK but desynced FCLK has more bandwidth
examples:
DDR5-7200 2:1 + 1800FCLK (this is unfortunately very slow)
DDR5-7600 2:1 + 1900FCLK (viable alternative to DDR5-6200 1:1) (requires good mobo)
DDR5-7800 2:1 + 1950FCLK (competitve with DDR5-6400 1:1) (requires good mobo)
DDR5-8000 2:1 + 2000FCLK (faster than DDR5-6400 1:1) (general hard to run)
DDR5-8100/8200/8300 can't sync :(
DDR5-8400 2:1 + 2100FCLK (unlikely to ever work)
Adjusting VDDG IOD and VDDG CCD can sometimes fix FCLK stability if it's just barely unstable. However due to the error connection this is extremely tidious to do.
Unified Memory Controller (UCLK)
clocks: 3000-3300MHz
scales with VSOC and pretty much nothing else
if you can't get a UCLK to work at 1.3V SOC it's just not gonna work and you should give up.
Really bad CPUs need more than 1.2VSOC for 3000MHz UCLK
Really good CPUs run 3300MHz at less than 1.3VSOC
100MHz more UCLK usually needs 100+mv more
example:
1.05VSOC >> 3000MHz UCLK stable
~1.15VSOC >> 3100MHz UCLK stable
~1.25VSOC >> 3200MHz UCLK stable
1.3VSOC >> 3300MHz UCLK UNSTABLE
in 2:1 mode the UCLK is so low that you can run some extremely VSOC voltages like 0.85-1.05V
one upside to doing this is that if you're on the stock power limit there's more power available to the cores
DRAM/PHY (MCLK) !still WIP!
clocks: upto 4000MHz+
Affected by VDDIO and VDDQ and VDDP
VDDIO VDDQ and VDDP all have sweet spots especially when pushing high MCLK in 2:1
VDDIO is the CPU's IO voltage.
- 1.1-1.5V depend on the motherboard
- I'd start with 1.4V usually and then move it up and down by 50mv
VDDQ is the DRAM's IO voltage
-1.1-1.65V depending on the motherboard and DIMMs
- I'd start with 1.4V usually and then move it up and down by 50mv
VDDP is internal to the CPU not sure what it's for but the P stands for PHY
- 0.9-1.15V depending on clocks and motherboard
